Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications

ABSTRACT

Methods of fabricating highly conductive regions in semiconductor substrates for radio frequency applications are used to fabricate two structures: (1) a first structure includes porous Si (silicon) regions extending throughout the thickness of an Si substrate that allows for the subsequent formation of metallized posts and metallized moats in the porous regions; and (2) a second structure includes staggered deep V-grooves or trenches etched into an Si substrate, or some other semiconductor substrate, from the front and/or the back of the substrate, wherein these V-grooves and trenches are filled or coated with metal to form the metallized moats.

CROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit under 35 U.S.C. §119(e) ofthe following co-pending and commonly-assigned U.S. Provisional PatentApplication Serial No. 60/331,854, entitled “METHODS OF FABRICATINGHIGHLY CONDUCTIVE REGIONS IN SEMICONDUCTOR SUBSTRATES FOR RADIOFREQUENCY APPLICATIONS,” filed on Nov. 20, 2002, by KingNing Tu, Ya-HongXie and Chang-Ching Yeh, Attorney Docket No. 30435.136-US-P1, whichapplication is incorporated by reference herein.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The invention relates to fabricating semiconductor devices, andmore particularly, to methods of fabricating highly conductive regionsin semiconductor substrates for radio frequency applications.

[0004] 2. Description of the Related Art

[0005] It has been a recent trend in the Si (silicon) integrated circuitindustry to integrate radio transmitters and other radio frequency (RF)devices onto digital integrated circuits. Such integration requires RFshielding to prevent interference with other noise sensitive portions ofthe integrated circuits.

[0006] Oxidized porous Si has been used to provide effective DC (directcurrent) isolation. However, oxidized porous Si cannot be made too thickbecause of the thermal expansion coefficient mismatch between oxidizedporous Si and Si. Therefore, it cannot be used for effective RFshielding, similar to silicon nitride and silicon dioxide films. On theother hand, the use of unoxidized porous Si as an insulating materialhas been successful in reducing RF crosstalk to a level identical tothat across a vacuum.

[0007] However, there is a need in the art to further reduce crosstalkfor high-end RF applications. The present invention satisfies that need.

SUMMARY OF THE INVENTION

[0008] The present invention describes methods of fabricating highlyconductive regions in semiconductor substrates for radio frequencyapplications. These methods are used to fabricate two structures: (1) afirst structure includes porous Si regions extending throughout thethickness of an Si substrate that allows for the subsequent formation ofmetallized posts and metallized moats in the porous regions; and (2) asecond structure includes staggered deep V-grooves or trenches etchedinto an Si substrate, or some other semiconductor substrate, from thefront and/or the back of the substrate, wherein these V-grooves andtrenches are filled or coated with metal to form the metallized moats.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Referring now to the drawings in which like reference numbersrepresent corresponding parts throughout:

[0010]FIG. 1 illustrates a structure for incorporating highly conductivemetallic regions into semiconductor substrates according to thepreferred embodiment of the present invention;

[0011]FIG. 2 illustrates an alternative embodiment of FIG. 1, wherein ahighly conductive metallized moat is formed by staggered deep V-groovesetched into the substrate;

[0012]FIG. 3 illustrates an alternative embodiment of FIG. 1, wherein ahighly conductive metallized moat is formed by a deep trench etched intothe substrate;

[0013]FIGS. 4A, 4B and 4C are cross-sectional side views of thestructures of FIGS. 1, 2 and 3, respectively;

[0014]FIG. 5 is a flowchart illustrating the process steps used increating metallized porous Si regions according to the preferredembodiment of the present invention;

[0015]FIG. 6 is a flowchart illustrating the process steps used increating V-grooves for a metallized moat according to the preferredembodiment of the present invention; and

[0016]FIG. 7 is a flowchart illustrating the process steps used increating trenches for a metallized moat according to the preferredembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0017] In the following description of the preferred embodiment,reference is made to the accompanying drawings which form a part hereof,and in which is shown by way of illustration a specific embodiment inwhich the invention may be practiced. It is to be understood that otherembodiments may be utilized and structural changes may be made withoutdeparting from the scope of the present invention.

[0018]FIG. 1 illustrates a structure for incorporating highly conductivemetallic regions into semiconductor substrates according to thepreferred embodiment of the present invention. A Si substrate 10 isdivided into a noisy circuit area 12 and a noise sensitive circuit area14, which are separated by a metallized moat 16. The highly conductivemetallized moat 16 is formed from metallized porous Si regions extendingthrough the thickness of the substrate 10. The noisy circuit area 12also includes metallized posts 18, created from metallized, localizedporous Si regions and extending through the thickness of the substrate10, wherein the metallized posts 18 act as “true ground” points.

[0019]FIG. 2 illustrates an alternative embodiment of FIG. 1, whereinthe highly conductive metallized moat 16 is formed by staggered deepV-grooves etched into the Si substrate 10, from both the front and theback of the substrate 10, wherein these V-grooves are filled with metal.

[0020]FIG. 3 illustrates an alternative embodiment of FIG. 1, whereinthe highly conductive metallized moat 16 is formed by a deep trenchetched into one side (either front or back side) of the Si substrate 10,wherein the trench is also filled with metal.

[0021]FIGS. 4A, 4B and 4C are cross-sectional side views of thestructures of FIGS. 1, 2 and 3, respectively. FIG. 4A illustrates themetallized porous Si regions 16 or 18 extending through the substrate10, FIG. 4B illustrates the staggered deep V-grooves 16 etched into theSi substrate 10 from both the front and the back of the substrate 10,and FIG. 4C illustrates the deep trench 16 etched into one side of theSi substrate 10.

[0022] Within the realm of integrated circuit technology, there are twopotential applications using the present invention. Both applicationsaddress important issues associated with mixed-signal integratedcircuits, which comprise a family of newly emerged type of integratedcircuits that is used for cellular telephones, portable electronics,high speed modems, and data storage devices, such as computer harddrives.

[0023] A first application provides one or more metallized posts 18 onthe substrate as low impedance paths to ground which is typicallylocated at the backside of the chip. These posts 18 can be used as “trueground” points, i.e. points with very low impedance contact to theground potential outside the chip, across the substrate 10. Such posts18 have very short paths to ground points, as compared to typical groundlines in conventional Si integrated circuit technology. As a result,these posts 18 have much lower impedance to ground, especially for highfrequency signals.

[0024] A second application creates the metallized moat 16 from ametallized porous Si region. Alternatively, the second applicationcreates the metallized moat 16 by etching deep V-grooves or trenches inthe Si substrate 10 and then depositing metals in the V-grooves orelectroplating the trenches. In this second application, the metallizedmoat 16 shields the noise sensitive circuits 14 from high frequencynoise generated by the noisy circuits 12. The metallized moat 16, inessence, creates a conducting cage, which is an electromagnetic shieldthat reduces RF crosstalk between the circuits 12 and 14.

[0025] As noted above, metallized porous Si regions can be used for boththe first and second applications, whereas the metal-filled deepV-grooves and trenches are more suited for the noise isolation of thesecond application. Moreover, while the preferred embodiment uses Sisubstrates, other semiconductor substrates, such as GaAs (galliumarsenide) and InP (indium phosphide), may be used in alternativeembodiments, especially in applications involving the V-grooves andtrenches.

[0026]FIG. 5 is a flowchart illustrating the process steps used increating the metallized porous Si regions according to the preferredembodiment of the present invention.

[0027] Block 20 represents the formation of porous Si regions beingperformed by anodization, which is a well-known art that was firstinvented about half a century ago. In this step, the surface of the Sisubstrate is exposed to HF (hydrogen fluoride) containing anelectrolyte. Porous Si forms into the Si substrate when an electricalcurrent is passed through the Si-electrolyte interface with the Sisubstrate acting as the anode. Adjusting the HF concentration in theelectrolyte and the current density during anodization alters themicrostructure of the porous Si region so formed.

[0028] Block 22 represents the metallization of the porous Si regionsbeing performed. The porous Si regions, with their interconnected pores,provide an excellent skeleton for metal deposition. Metals can beintroduced into the porous Si regions in a number of different ways: byvapor deposition, solid state interdiffusion and reaction, and liquidstate penetration. Because the porous Si regions each have a very largeinterconnected internal surface area, a capillary effect can be used tofacilitate the penetration of any low melting point molten metal thatwets the surface of the Si substrate throughout the entire porous Siregion.

[0029] Two metals that fit the low melting point requirement are Au(gold) and Al (aluminum). The eutectic point of Au—Si is 370 degrees C.and that of Al—Si is 577 degrees C. Both metals are acceptable withrespect to processing of integrated circuit devices on Si substrates.

[0030] Since Au is a deep trap impurity in Si, the Au penetration isfollowed with a penetration by molten Sn (tin) or an Sn-based solder. Snwill fill up the pores of the porous Si regions. Moreover, Sn serves theimportant function of retaining Au from outdiffusion, because of Au—Snintermetallic compound formation. Sn also provides mechanical strengthto the otherwise porous structure.

[0031]FIG. 6 is a flowchart illustrating the process steps used increating the V-grooves for the metallized moat 16 according to thepreferred embodiment of the present invention.

[0032] Block 24 represents the V-grooves being created along a [110]direction on an (001) surface of the Si substrate can be created usingstandard lithography techniques, followed by an anisotropic wet etchingin solutions such as KOH (potassium hydroxide). The step may prepareV-grooves on both surfaces of the Si substrate for isolation purposes.The width of the V-groove is selected to give a depth of the V-groovethat is about half the thickness of the substrate.

[0033] Block 26 represents the metallization of the V-grooves beingperformed. A lift-off process is used to deposit a multilayer metallicthin film (the total thickness of which is preferably on the order of afew hundred nanometers) into the V-grooves. For example, a trilayer ofCr/Cu/Au (chromium/copper/gold) or Ti/Ni/Pd (titanium/nickel/palladium)can be used. The resulting structure can be strengthened by a flow ofmolten solder into the V-grooves using a horizontal capillary effect.The solder may be Pb-free (lead-free) alloys such eutectic SnAg(tin-silver) or SnAgCu (tin-silver-copper) with a melting point around220 degrees C.

[0034]FIG. 7 is a flowchart illustrating the process steps used increating the trenches for the metallized moat 16 according to thepreferred embodiment of the present invention.

[0035] Block 28 represents the trenches being created along a [110]direction on an (001) surface of the Si substrate can be created usingstandard lithography techniques, followed by an anisotropic wet etchingin solutions such as KOH.

[0036] Block 30 represents the metallization of the trenches beingperformed. Preferably, the Cu is deposited into the trenches byelectro-plating or chemical vapor deposition (CVD). The entire trenchcan be filled with Cu, or a layer of Cu can be deposited and the rest ofthe trench filled with molten solder.

[0037] Conclusion

[0038] This concludes the description of the preferred embodiment of theinvention. The foregoing description of one or more embodiments of theinvention has been presented for the purposes of illustration anddescription. It is not intended to be exhaustive or to limit theinvention to the precise form disclosed. Many modifications andvariations are possible in light of the above teaching. It is intendedthat the scope of the invention be limited not by this detaileddescription, but rather by the claims appended hereto.

What is claimed is:
 1. A method of fabricating highly conductive regionsin semiconductor substrates for radio frequency applications,comprising: forming one or more porous Si (silicon) regions on a Sisubstrate by anodization; and depositing one or more metals into theporous Si regions.
 2. The method of claim 1, wherein the forming stepcomprises: exposing a surface of the Si substrate to HF (hydrogenfluoride) containing an electrolyte; and passing an electrical currentthrough a Si-electrolyte interface with the Si substrate acting as theanode in order to form the porous Si regions on the Si substrate.
 3. Themethod of claim 2, further comprising adjusting the HF concentration inthe electrolyte and the electrical current density during anodization toalter a microstructure of the porous Si regions.
 4. The method of claim1, wherein the metals are deposited into the porous Si regions by vapordeposition, solid state interdiffusion and reaction, or liquid statepenetration.
 5. The method of claim 1, wherein the metal is Au (gold) orAl (aluminum).
 6. The method of claim 5, wherein a penetration by Au isfollowed with a penetration by molten Sn (tin) or an Sn-based solder. 7.A method of fabricating highly conductive regions in semiconductorsubstrates for radio frequency applications, comprising: creating a moaton a surface of a Si (silicon) substrate using standard lithographytechniques, followed by an anisotropic wet etching; and depositing amultilayer metallic thin film into the moat.
 8. The method of claim 7,wherein the moat is comprised of one or more V-grooves created along a[110] direction on an (001) surface of the Si substrate.
 9. The methodof claim 7, wherein the V-grooves are prepared on both surfaces of theSi substrate for isolation purposes.
 10. The method of claim 7, whereinthe V-groove's width is selected to give a depth of the V-groove that isabout half the thickness of the Si substrate.
 11. The method of claim 7,wherein the anisotropic wet etching is performed in a solution of KOH(potassium hydroxide).
 12. The method of claim 7, wherein the multilayermetallic thin film is a trilayer of Cr/Cu/Au (chromium/copper/gold) orTi/Ni/Pd (titanium/nickel/palladium).
 13. The method of claim 7, furthercomprising strengthening the V-grooves by a flow of molten solder intothe V-grooves using a horizontal capillary effect.
 14. The method ofclaim 7, wherein the solder is a lead-free alloy such as eutectic SnAg(tin-silver) or SnAgCu (tin-silver-cooper).
 15. The method of claim 7,wherein the moat is comprised of one or more trenches.
 16. The method ofclaim 7, wherein the multilayer metallic thin film comprises Cu(copper).
 17. The method of claim 16, wherein the trench is filledentirely with Cu.
 18. The method of claim 16, wherein the trench isplated with a layer of Cu and then filled with molten solder.
 19. Themethod of claim 16, wherein the Cu is electro-plated into the trenches.20. The method of claim 16, wherein the Cu is deposited by chemicalvapor deposition (CVD).
 21. A structure for incorporating highlyconductive metallic regions into a semiconductor substrate, comprising:a Si (silicon) substrate having one or more metallized posts, formedfrom metallized, localized porous Si regions, that provide low impedancepaths to ground.
 22. A structure for incorporating highly conductivemetallic regions into a semiconductor substrate, comprising: a Si(silicon) substrate divided into a noisy circuit area and a noisesensitive circuit area, wherein the noisy circuit area and a noisesensitive circuit area are separated by a metallized moat formed frommetallized porous Si regions.
 23. A structure for incorporating highlyconductive metallic regions into a semiconductor substrate, comprising:a Si (silicon) substrate divided into a noisy circuit area and a noisesensitive circuit area, wherein the noisy circuit area and a noisesensitive circuit area are separated by a metallized moat formed by oneor more deep V-grooves etched into the Si substrate, from both the frontand the back of the Si substrate, wherein the V-grooves are filled withmetal.
 24. A structure for incorporating highly conductive metallicregions into a semiconductor substrate, comprising: a Si (silicon)substrate divided into a noisy circuit area and a noise sensitivecircuit area, wherein the noisy circuit area and a noise sensitivecircuit area are separated by a metallized moat formed by one or moredeep trenches etched into one side of the Si substrate, wherein thetrench is filled with metal.
 25. The structure of claim 24, wherein thedeep V-grooves are staggered.